In a field-effect transistor like a high electron mobility transistor (hereinafter referred to as HEMT) made of a compound semiconductor, such as gallium arsenide (GaAs), a gate electrode having a short length and a low resistance is required to enhance the characteristics of the transistor. A gate electrode having a T-shaped cross-section meets this requirement and various methods for producing such a gate electrode have been proposed.
FIG. 3 is a cross-sectional view of a prior art field-effect transistor, produced with reference to a method for producing a gate electrode disclosed in Japanese Published Patent Application No. Sho. 61-77370. In FIG. 3, reference numeral 31 designates a semi-insulating GaAs substrate. A high dopant purity GaAs buffer layer 32 is disposed on the substrate 31. An n type AlGaAs layer 33 is disposed on the buffer layer 32. A high concentration n type (hereinafter referred to as n.sup.+ type) GaAs layer 34 is disposed on the AlGaAs layer 33. Ohmic electrodes 35 serving as source and drain electrodes are disposed on the n.sup.+ type GaAs layer 34 opposite to and spaced from each other by a prescribed interval. A stripe-shaped recess groove 36 penetrates a prescribed portion of the n.sup.+ type GaAs layer 34 between the ohmic electrodes 35. A gate electrode 37 having a T-shaped cross-section is disposed on the AlGaAs layer 33 which is exposed on the bottom surface of the recess groove 36. A two-dimensional electron gas layer 38 is formed in the buffer layer 32 in the vicinity of the boundary with the AlGaAs layer 33, in which electrons supplied from the AlGaAs layer 33 are stored.
FIGS. 4(a) to 4(f) are cross-sectional views of process steps for producing the field effect transistor of FIG. 3.
First of all, as shown in FIG. 4(a), a GaAs buffer layer 32, an n type AlGaAs layer 33, and an n.sup.+ type GaAs layer 34 are successively epitaxially grown on the semi-insulating GaAs substrate 31. Then, ohmic electrodes 35 are formed on the n.sup.+ type GaAs layer 34 opposite to and spaced from each other by a prescribed interval, by deposition and lift-off using a photoresist, as shown in FIG. 4(b).
Then, as shown in FIG. 4(c), on the n.sup.+ type GaAs layer 34 having the ohmic electrodes 35, a lower resist film 40 approximately 2000 angstroms thick and an upper resist film 41 approximately 1 micron thick are successively deposited. The upper resist film 41 has a high sensitivity and the lower resist film 40 has a sensitivity lower than that of the upper resist film 41.
Then, the lower and upper resist films 40 and 41 on the ohmic electrodes 35 are exposed in a stripe shape by an electron beam exposure method, forming a pattern of a gate electrode. If the amount and intensity of the electron beam are made large at the center of the gate pattern and small at the both sides of the gate pattern, both of the upper and lower resist films 41 and 40 are exposed at the center of the gate pattern while only the upper resist film 41 is exposed at the both sides of the gate pattern, resulting in the lower resist 40 and the upper resist 41 shown in FIG. 4(d).
Then, the n.sup.+ type GaAs layer 5 is etched by wet etching using the lower resist film 40 as a mask to form a recess groove 36. Thereafter, a gate metal 45 is deposited on the entire surface of the wafer as shown in FIG. 4(e).
Then, the gate metal 45 on the upper resist film 41 is removed together with the resist films 41 and 40 by a lift-off technique, resulting in a field effect transistor shown in FIG. 4(f).
According to this conventional method, the high sensitivity upper resist film and the low sensitivity lower resist film are patterned by the electron beam exposure whose amount and intensity are varied on the resist films and then the gate metal is formed by metal deposition and lift-off. Therefore, a fine T-shaped gate is formed in a simple process and an increase in the gate resistance due to a reduced gate length is suppressed, resulting in a high performance field-effect transistor even at high frequencies.
However, when the photoresist is deposited on the n.sup.+ type GaAs layer 34 in the step of FIG. 4(c), since the ohmic electrodes 35 are present, the step difference causes non-uniformity in the thickness of the photoresist, reducing the patterning precision of the photoresist. Further, in the step of FIG. 4(d), the gate-to-source distance may vary due to mask alignment error or the like, inviting variation in the characteristics of the completed devices.
FIGS. 5(a) to 5(h) are cross-sectional views in process steps for producing a field effect transistor using a production method for a gate electrode disclosed in Japanese Published Patent Application No. Hei. 3-21032.
First of all, a semiconductor substrate having an active region is prepared. Then, as shown in FIG. 5(a), a photoresist film 51 approximately 2000 angstroms thick is formed on the substrate 50 and a polyimide film 52 approximately 10000 angstroms thick is formed thereon.
As shown in FIG. 5(b), an aluminum film 53 approximately 500 angstroms thick having a stripe-shaped aperture 54 whose width corresponds to a gate length is formed on the polyimide film 52 using deposition and lift-off.
Then, the polyimide film 52 and the photoresist film 51 are etched by dry etching using an O.sub.2 plasma and using the aluminum film 53 as a mask to form an aperture 55 as shown in FIG. 5(c).
Thereafter, the wafer is immersed in a mixture of ethylenediamine and hydrazine to etch away the polyimide film 52, whereby the aperture 55 of the polyimide film 52 is widened as shown in FIG. 5(d).
Then, the aluminum film 53 is etched using a solution comprising H.sub.3 PO.sub.4 and H.sub.2 O as shown in FIG. 5(e).
As shown in FIG. 5(f), a gate metal 56, such as Ti/Pt/Au, is deposited on the entire surface of the wafer.
Thereafter, the gate metal on the polyimide film 52 is removed together with the polyimide film 52 and the photoresist film 51 by a lift-off technique using an acetone solution, resulting in a T-shaped gate comprising a base part 57 and a head part 58 shown in FIG. 5(g). Since the head part 58 of the gate is formed utilizing selective etching of the polyimide film 52, the head part 58 does not deviate from the base part 57.
Finally, as shown in FIG. 5(h), an Au system metal 59 is deposited on the entire surface of the wafer and then the metal 59 on the semiconductor substrate 50 is alloyed with the semiconductor by annealing to form source and drain electrodes which ohmic contact with the semiconductor.
According to this conventional method, since the source and drain electrodes are formed self-alignedly with the gate electrode, the gate-to-source distance does not vary, so that the characteristics of the device do not deteriorate. In addition, the gate-to-source distance can be shorter than the precision of the mask alignment, resulting in a high performance device having a reduced gate-to-source resistance. Further, since the metal 59 deposited on the gate electrode has a lower resistivity than that of the T-shaped gate comprising the base part 57 and the head part 58, this metal 59 reduces the gate electrode resistance, enhancing the high frequency characteristic of the device.
When a field effect transistor is manufactured in accordance with the process steps shown in FIGS. 5(a) to 5(h), in order to further reduce the gate resistance to enhance the device characteristics, the metal layer 59, which is deposited on the lower T-shaped gate electrode, may be thicker. In this case, the ohmic electrodes 35, which are deposited with the metal layer 59, unfavorably become thick and may be short-circuited to the lower gate electrode 57 as shown in FIG. 6. As a result, the gate resistance cannot be sufficiently reduced. If the photoresist film 51 is made thicker to heighten the base part 57 of the T-shaped gate, the thick ohmic electrodes 35 may not be short-circuited with the gate electrode. However, since metal is accumulated perpendicular to the plane surface of the substrate during vapor deposition, it is impossible to form the photoresist film 51 thicker than the deposited gate metal 56. That is, there is a limitation to the reduction in gate resistance according to this method.
In addition, a metal deposition is required twice in the method of FIGS. 4(a)-(4f) and 5(a)-5(h), thereby complicating the production process.